A Redundant Approach to Increase Reliability of Data Cache Memories

In this work, we propose architectural solutions to cope with permanent faults in cache memories. The approach uses a FIFO and a redundant cache to detect and tolerate permanent faults in caches. During a write operation, the word is written at the same time in cache and in FIFO. A comparison is performed to evaluate if the duplicated word has the same value in both memories. In case there is a divergence between compared values, the cache line is set as faulty and it will not be used for reading or writing operations. Additionally, the word written in FIFO is copied to the redundant cache and all accesses related to the faulty address in main cache are forwarded to the redundant cache. The proposed solution was implemented using two different mapping techniques. In the first case, the main cache uses set-associative mapping with LRU replacement policy. In the second case, the main cache combines set-associative mapping, LRU and a round robin policy to reduce the number of write-back operations. In both cases, the redundant cache uses direct mapping. The proposed solution was validated using a VHDL implementation and FPGA prototyping. Simulation results show that with the proposed models is possible to obtain hit rates between 95% and 99%, even when the cache memory presents faults in up to 80% of their lines.

Automated summary

The study proposes architectural solutions to handle permanent faults in cache memories, utilizing FIFO and redundant cache for fault detection and tolerance. Experimental results demonstrate that hit rates between 95% and 99% can be achieved even when up to 80% of cache memory lines have faults.