期刊
2D MATERIALS
卷 4, 期 1, 页码 -出版社
IOP PUBLISHING LTD
DOI: 10.1088/2053-1583/4/1/011008
关键词
graphene; atomic layer deposition; device integration; hysteresis; air stability; Al2O3
资金
- EPSRC [EP/K016636/1, EP/L020963/1]
- ERC [279342]
- Churchill College, Cambridge
- NUDT
- ESPRC [EP/L016087/1, EP/M506485/1]
- Conacyt Cambridge Scholarship
- Roberto Rocca Fellowship
- EPSRC [EP/K016636/1, EP/L020963/1] Funding Source: UKRI
- Engineering and Physical Sciences Research Council [EP/L020963/1, EP/K016636/1, 1463937, 1578379] Funding Source: researchfish
We demonstrate a simple, scalable approach to achieve encapsulated graphene transistors with negligible gate hysteresis, low doping levels and enhanced mobility compared to as-fabricated devices. We engineer the interface between graphene and atomic layer deposited (ALD) Al2O3 by tailoring the growth parameters to achieve effective device encapsulation whilst enabling the passivation of charge traps in the underlying gate dielectric. We relate the passivation of charge trap states in the vicinity of the graphene to conformal growth of ALD oxide governed by in situ gaseous H2O pretreatments. We demonstrate the long term stability of such encapsulation techniques and the resulting insensitivity towards additional lithography steps to enable vertical device integration of graphene for multi-stacked electronics fabrication.
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