High temperature stability embedded ReRAM for 2x nm node and beyond

We report the performances and reliability of our ReRAM technology integrated in 28nm node. Low raw BER approaching 10(-5) without ECC or redundancy is achieved. 10(6) cycles endurance without significant window degradation is shown. We report stable memory window after 15h bake at 210 degrees C after 10kcycles, which is one of the best results reported so far to our knowledge. Technology passed basic (3x reflow) and extended (9 cycles) SMT tests with zero failures. Bitcell and memory stack engineering improved the window margin statistics. Optimized forming protocols are developed to increase memory yield over cycling. Program and verify algorithms allowed to insure no overlap between high and low resistive states on 1Mb arrays.

Automated summary

This study reports the performances and reliability of ReRAM technology integrated in the 28nm node. The technology achieved low raw BER and showed good endurance with stable memory window even after high temperature baking.