An LNA with Input Power Match from 6.1 to 38.6 GHz, the Noise-Figure Minimum of 1.9 dB, and Employing Back Gate for Matching

This paper proposes using the back-gate terminal of an FDSOI transistor for input power matching. This concept is experimentally demonstrated with a 22-nm FDSOI low-noise amplifier (LNA). Thanks to the real part of the back-gate impedance, the LNA vertical bar S-11 vertical bar < -10-dB bandwidth extends from 6.1 to 38.6 GHz. In addition, applying input to both the front- and back-gate terminals, as well as employing a current-reuse configuration, increases the effective transconductance of the LNA first stage, thereby increasing its gain and lowering its input-referred noise. As a result, the LNA is able to achieve 12.2 +/- 3.4 dB of gain, -13 dBm of IP1dB, and a noise-figure minimum of 1.9 dB while consuming 7.8 mW of power and occupying 0.03-mm(2) of active area.

Automated summary

This paper proposes using the back-gate terminal of an FDSOI transistor for input power matching. It is experimentally demonstrated with a 22-nm FDSOI low-noise amplifier (LNA). By applying input to both the front- and back-gate terminals and employing a current-reuse configuration, the LNA is able to increase its gain and lower its input-referred noise.