Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon

For the first time, a reliability study on degradation of InGaAs/GaAs nano-ridge p-i-n diodes monolithically integrated on Si by nano-ridge engineering (NRE) is reported. Wafer-level constant current stress in forward bias shows a gradual power law aging of both forward and dark current. Current crowding and Joule heating near the p-contact are responsible for the degradation in forward bias region. Indications of defect formation and Ti diffusion at the metal/GaAs interface are witnessed. The electrical stress-induced leakage current builds up at reverse bias region, pointing to the degradation of crystal quality. A sintering process lowers the p-contact resistance and improves electrical stability. The high aspect-ratio of the trenches leads to effective threading dislocation trapping: no dislocations have been observed to penetrate the active region during the 5000s stress time. This early work sheds light on realizing electrically robust GaAs diodes on Si and reliable monolithic lasers.

Automated summary

This study reports for the first time a reliability study on degradation of InGaAs/GaAs nano-ridge p-i-n diodes monolithically integrated on Si by nano-ridge engineering (NRE). The results show that current crowding and Joule heating near the p-contact are responsible for the degradation in forward bias region, while the electrical stress-induced leakage current indicates the degradation of crystal quality in reverse bias region. The study also demonstrates that a sintering process can lower the p-contact resistance and improve electrical stability, and the high aspect-ratio of the trenches leads to effective threading dislocation trapping.