Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error

Floating-point division involves the computation of the ratio (1 + Mx)/(1 + My), where Mx and My represents the mantissas of the input values. In this paper, we propose a new method for approximating this operation using a linear function of Mx, with coefficients that depend on My. The coefficients are calculated to minimize the Mean Relative Error Distance (MRED) of the approximation. To this end, the range of My is partitioned in N sub-intervals where the minimization of MRED is formulated as a linear programming problem, whose solution gives optimal coefficient values. The hardware implementation requires a small lookup table, two multipliers and an adder. An aggressive coefficients quantization is exploited to further optimize the design. Obtained MRED improves by increasing N , ranging from 1.4% to 0.33%. Implementation results in a 28nm CMOS technology show that the proposed design outperforms the state-of-the-art, offering the best trade-off between hardware complexity and accuracy. Results for two image processing applications, change detection and JPEG compression, demonstrate remarkable performance, with SSIM very close to 1 and PSNR values exceeding 50dB.

Automated summary

This paper proposes a new method for approximating floating-point division by calculating coefficients to minimize the Mean Relative Error Distance (MRED). The hardware implementation uses a lookup table, multipliers, and an adder, with an aggressive coefficients quantization to optimize the design. The results show that the proposed design outperforms the state-of-the-art, offering the best trade-off between hardware complexity and accuracy, and achieves remarkable performance in image processing applications.