4.8 Article

Integrated Circuit for Magnetic Encoder Sensing in TMR-Based Industrial Positioning System

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IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2023.3321996

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Multichannel application-specific integrated circuit (ASIC); offset mitigation; positioning; tunnel magneto-resistance (TMR) sensors; variable gain instrumentation amplifier (VGIA)

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This article presents the design and implementation of a three-channel ASIC for signal acquisition in industrial positioning systems. The ASIC utilizes magnetic encoder scales and tunnel magneto-resistance (TMR) sensors for signal acquisition. It includes various features such as offset mitigation for Wheatstone bridge, programmable gain for instrumentation amplifier, and SAR ADC for signal digitization. The ASIC prototype is produced in XFAB 180-nm CMOS process and successfully meets the requirements of industrial applications.
This article presents the design and implementation of a three-channel ASIC for signal acquisition in industrial positioning systems that use magnetic encoder scales and tunnel magneto-resistance (TMR) sensors. The ASIC includes a mechanism to mitigate Wheatstone bridge offsets, an instrumentation amplifier with 5-bit programmable gain, and a 12-bit 2.5 MSps SAR ADC for signal digitization. The ASIC prototype is produced in XFAB 180-nm CMOS process. The ASIC can mitigate offsets up to approximately 1.3x VCM and amplify signals with a gain of 43.5 dB. The signal chain achieves an SNDR of 52 dB. The ASIC is fitted into a platform and tested with 5-mm pole pitch (PP) magnetic scales, correctly producing sin/cos signals used in typical positional algorithms. The implemented amplification allows the acquisition of practically undetectable signals at reading distances (RDs) 2x PP, which relaxes RD precision requirements under contaminated environments and increases the tolerance to mechanical vibrations. By performing on-chip A/D conversion, position information can be computed earlier in the signal chain through onboard digital-signal processors for enhanced signal integrity. Furthermore, to obtain a compact system suitable for various industrial applications, the three channels share a 6-wire LVCMOS output, i.e., a 6x reduction of the number of pins.

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