Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications

The increasing computational intensity of important new applications poses a challenge for their use in resource-restricted devices. Approximate computing using power-efficient arithmetic circuits is one of the emerging strategies to reach this objective. In this article, five hardware-efficient logarithmic floating-point (FP) multipliers are proposed, which all use simple operators, such as adders and multiplexers, to replace complex and more costly conventional FP multipliers. Radix-4 logarithms are used to further reduce the hardware complexity. These designs produce double-sided error distributions to mitigate error accumulation in complex computations. The proposed multipliers provide superior trade-offs between accuracy and hardware, with up to 30.8% higher accuracy than a recent logarithmic FP design or up to 68x less energy than the conventional FP multiplier. Using the proposed FP logarithmic multipliers in JPEG image compression achieves higher image quality than a recent logarithmic multiplier design with up to 4.7 dB larger peak signal-to-noise ratio. For training in benchmark NN applications, the proposed FP multipliers can slightly improve the classification accuracy while achieving 4.2x less energy and 2.2x smaller area than the state-of-the-art design.

Automated summary

This article proposes five hardware-efficient logarithmic floating-point multipliers, which use simple operators and radix-4 logarithms to reduce hardware complexity and achieve better trade-offs between accuracy and hardware. The proposed multipliers show superior performance in terms of image quality and accuracy in JPEG image compression and neural network applications, while consuming less energy and occupying smaller area compared to state-of-the-art designs.