3.8 Review

Fabrication and characterization of silicon-on-insulator wafers

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Article Nanoscience & Nanotechnology

Preparation of thin-film SOI wafer by low-dose ion implantation

Yuhang Zhang et al.

Summary: This paper investigates the preparation of silicon-on-insulator (SOI) devices by studying the separation by implanted oxygen process under low-dose implantation conditions using the two-step implantation method and internal thermal oxidation process. The effects of different types of silicon wafers and implantation doses on various properties of the SOI material are examined. Ultra-thin SOI wafers with low defect density and high breakdown voltage are successfully prepared.

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Characterization of Residual Stress in SOI Wafers by Using MEMS Cantilever Beams

Haotian Yang et al.

Summary: This paper proposes a low-cost method based on mechanical modeling to characterize the residual stresses in SOI wafers, which allows for the calculation of residual stress values based on beam deformation. Experimental determination of the residual strain in the MEMS beam and thus the residual stress in the SOI wafer was achieved using this method. The results were compared with calculations based on beam deflection, demonstrating the validity of this method. It provides valuable theoretical reference and data support for the design and optimization of devices based on SOI-MEMS technology, and offers a lower-cost solution for residual stress measurement technique applicable in various fields.

MICROMACHINES (2023)

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Large-Diameter III-V on Si Substrates by the Smart Cut Process: The 200 mm InP Film on Si Substrate Example

Bruno Ghyselen et al.

Summary: A new technology is proposed to extend the diameter of III-V materials by combining wafer bonding and layer transfer techniques with tiling. This approach involves rebuilding small diameter III-V substrates into large diameter wafers, allowing for cost-effective production of InP films with a diameter of 200 mm. This generic method can also be adapted to produce other large-diameter III-V on Si substrates, potentially reaching 300 mm in diameter.

PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE (2022)

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Waveguide coupled III-V photodiodes monolithically integrated on Si

Pengyan Wen et al.

Summary: This study successfully achieved the seamless integration of III-V nanostructures on silicon and demonstrated the performance of scaled and waveguide coupled III-V photodiodes. Furthermore, it was found that the temperature increase during device operation as an emitter was only approximately 15 K according to experimental and simulation results.

NATURE COMMUNICATIONS (2022)

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The advancement of silicon-on-insulator (SOI) devices and their basic properties

T. E. Rudenko et al.

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Hye-Lim Kang et al.

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W. Schwarzenbach et al.

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Study of high-temperature Smart Cut™: Application to silicon-on-sapphire films and to thin foils of single crystal silicon

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High quality extremely thin SOI fabricated by facilitated ion-cut with H-trapping effect

Yongwei Chang et al.

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Arnab Biswas et al.

APPLIED PHYSICS LETTERS (2014)

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Characterization of heavily doped SOI wafers under pseudo-MOSFET configuration

F. Y. Liu et al.

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Atomic Scale Thickness Control of SOI Wafers for Fully Depleted Applications

W. Schwarzenbach et al.

ADVANCED SEMICONDUCTOR-ON-INSULATOR TECHNOLOGY AND RELATED PHYSICS 16 (2013)

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Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

G. Servanton et al.

18TH MICROSCOPY OF SEMICONDUCTING MATERIALS CONFERENCE (MSM XVIII) (2013)

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Deformation of varifocal mirror with narrow frame by SOI wafer residual stress

Takashi Sasaki et al.

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Smart Cut™: Review on an attractive process for innovative substrate elaboration

H. Moriceau et al.

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Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX

Noel Rodriguer et al.

MICROELECTRONIC ENGINEERING (2011)

Article Engineering, Electrical & Electronic

Revisited Pseudo-MOSFET Models for the Characterization of Ultrathin SOI Wafers

Noel Rodriguez et al.

IEEE TRANSACTIONS ON ELECTRON DEVICES (2009)

Article Materials Science, Multidisciplinary

A comparison of the etching behaviour of the FS Cr-free SOI with that of the Secco etching solution on silicon-on-insulator substrates

Jochen Maehliss et al.

MATERIALS SCIENCE AND ENGINEERING B-ADVANCED FUNCTIONAL SOLID-STATE MATERIALS (2009)

Article Nanoscience & Nanotechnology

Characterization of ultrathin SOI film and application to short channel MOSFETs

Xiaohui Tang et al.

NANOTECHNOLOGY (2008)

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Study of HCl and secco defect etching for characterization of thick sSOI

A. Abbadie et al.

JOURNAL OF THE ELECTROCHEMICAL SOCIETY (2007)

Article Materials Science, Multidisciplinary

Properties of silicon nanolayers on insulator

O. V. Naumova et al.

MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY (2006)

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A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding

Xiaobo Ma et al.

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Single crystal silicon MEMS fabrication based on smart-cut technique

JG Du et al.

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Smart-Cut® technology:: from 300 mm ultrathin SOI production to advanced engineered substrates

C Maleville et al.

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Low defect density and planar patterned SOI materials by masked SIMOX

YM Dong et al.

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Frontiers of silicon-on-insulator

GK Celler et al.

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The generic nature of the Smart-Cut® process for thin film transfer

B Aspar et al.

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Hydrogen and helium bubbles in silicon

GF Cerofolini et al.

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Silicon-on-insulator:: materials aspects and applications

A Plössl et al.

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A review of the pseudo-MOS transistor in SOI wafers: Operation, parameter extraction, and applications

S Cristoloveanu et al.

IEEE TRANSACTIONS ON ELECTRON DEVICES (2000)

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Crystal originated particle induced isolation failure in Czochralski silicon wafers

JG Park et al.

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS (2000)