Tri-gate junctionless transistors with electrostatically highly doped channel

Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (V-gb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes.(c) 2023 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license(http://creativecommons.org/licenses/by/4.0/).

Automated summary

This paper demonstrates the performance of a tri-gate JLT with an electrostatically highly doped channel through numerical simulation, showing the potential of overcoming short-channel effects for sub-3-nm technology nodes.