A Practical Phase Gate for Producing Bell Violations in Majorana Wires

Carrying out fault-tolerant topological quantum computation using non-Abelian anyons (e.g., Majorana zero modes) is currently an important goal of worldwide experimental efforts. However, the Gottesman-Knill theorem [1] holds that if a system can only perform a certain subset of available quantum operations (i.e., operations from the Clifford group) in addition to the preparation and detection of qubit states in the computational basis, then that system is insufficient for universal quantum computation. Indeed, any measurement results in such a system could be reproduced within a local hidden variable theory, so there is no need for a quantum-mechanical explanation and therefore no possibility of quantum speedup [2]. Unfortunately, Clifford operations are precisely the ones available through braiding and measurement in systems supporting non-Abelian Majorana zero modes, which are otherwise an excellent candidate for topologically protected quantum computation. In order to move beyond the classically simulable subspace, an additional phase gate is required. This phase gate allows the system to violate the Bell-like Clauser-Horne-Shimony-Holt (CHSH) inequality that would constrain a local hidden variable theory. In this article, we introduce a new type of phase gate for the already-existing semiconductor-based Majorana wire systems and demonstrate how this phase gate may be benchmarked using CHSH measurements. We present an experimentally feasible schematic for such an experiment using a measurement-only approach that bypasses the need for explicit Majorana braiding. This approach may be scaled beyond the two-qubit system necessary for CHSH violations, leading to a well-defined platform for universal fault-tolerant quantum computation using Majorana zero modes.