W-IQ: Wither-logic based issue queue for RISC-V superscalar out-of-order processor

The rise of RISC-V Instruction Set Architecture (ISA) motivates research on improving the performance of the RISC-V processors. Issue Queue (IQ) is an essential factor affecting the Instructions Per Clock (IPC) and delay. This paper proposes a Withering-logic Based Issue Queue (W-IQ) to improve IPC while reducing the delay. We further evaluate the IPC of W-IQ with the XCVU440 FPGA. The average running time of the SPEC2006 of the W-IQ is 34% shorter than that of the non-compaction IQ with position-based selection logic. Furthermore, for a 65 nm CMOS process, the W-IQ delay is 27% lower than compaction IQ with the serial age-aware selection logic.

Automated summary

This paper proposes a Withering-logic Based Issue Queue (W-IQ) to improve the performance of RISC-V processors by increasing IPC and reducing delay. Experimental results show that W-IQ outperforms traditional methods in terms of running time and delay.