4.8 Article

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping

期刊

NANO LETTERS
卷 23, 期 23, 页码 11345-11352

出版社

AMER CHEMICAL SOC
DOI: 10.1021/acs.nanolett.3c04009

关键词

2D semiconductors; oxygen plasma; dual-gate; tungsten oxide; patterning doping profiles; transferred vdW top-gate

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This study presents a novel approach to overcome the challenges faced by 2D materials in CMOS technology, specifically in the production of high-performance p-type field effect transistors (p-FETs). By fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks and utilizing selective oxygen plasma-doping, the researchers achieve exceptional electrostatic controllability and low power consumption in PMOS inverters.
The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

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