Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations

We report TCAD simulation studies on nanowire (NW), nanosheet (NS) and forksheet (FS) FET hot-carrier reliability. The simulations entail i) solving the Boltzmann transport equation to obtain the distribution of carriers over energy in the devices, ii) calculation of interface state generation at the channel/gate stack interface and charging of bulk defects in dielectrics, and iii) evaluation of how the generated/trapped charges affect the FET I-V. We discuss the models used in state-of-the-art hot-carrier simulation flows, anneal measurements to probe hot-carrier induced interface defects, the validity of the simulation models in the (V-g,V-d) bias space by comparing simulations to NW FET measurements and the conclusions the hot-carrier simulations provide for NS and FS FETs.

Automated summary

We present TCAD simulation studies on the hot-carrier reliability of nanowire (NW), nanosheet (NS), and forksheet (FS) FETs. The simulations involve solving the Boltzmann transport equation, calculating interface state generation and bulk defect charging, and evaluating the impact of generated/trapped charges on FET characteristics. We discuss the models used in hot-carrier simulation flows, anneal measurements, and validate the simulation models by comparing with NW FET measurements, providing insights for NS and FS FETs.