Board-Level Drop Impact Reliability of Silicon Interposer-Based 2.5-D IC Integration

This paper is a theoretical and experimental assessment of the solder joint reliability of an advanced high-density interposer-based 2.5-D IC integration technology on-board under drop impact in accordance with the JEDEC standard. Focus is placed on the influences of underfill on the solder joint reliability. The transient dynamic responses of the packaging technology are simulated using Input-G finite element analysis, with the use of the Johnson-Cook model for describing the constitutive behaviors of the solder interconnect materials. Furthermore, an energy-based model is utilized for predicting the drop impact solder joint fatigue life. The effectiveness of the proposed theoretical models is demonstrated through comparison with the drop test experiment. Finally, the effects of some essential factors including the allowed JEDEC shock pulse tolerances are examined in order to establish a design guideline for enhanced shock resistance capability. Results show that underfill and even partial underfill can significantly improve the drop impact solder joint reliability of the 2.5-D IC integration technology. The solder joint reliability turns out to be considerably affected by the shock pulse tolerances, suggesting that there is a crucial need to regularly calibrate the precision of drop testers for minimizing the prediction uncertainty.