期刊
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
卷 6, 期 6, 页码 946-953出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCPMT.2016.2527793
关键词
3-D integration; 3-D stacking; bonding; packaging; self-alignment
3-D stacking with vertical interconnection of thinned microelectronic silicon chips is a novel approach to achieve the enhanced performance, higher density, and smaller size of integrated circuits with a better multifunctionality than the traditional 2-D chip packaging. To achieve this, high alignment accuracy is required between the top chip and the bottom substrate along with good bonding between the two intermediate surfaces. In this paper, a novel approach to stacking is proposed: rapid heating self-aligned assembly. Using this approach, fast and good intermediate dielectric bonding is realized along with high alignment accuracy between the top chip and the bottom substrate compared with the similar process at room temperature. This approach can be used for die-to-die bonding and die-to-wafer bonding for 3-D and MEMS applications.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据