OPTIMIZATION OF THE THERMAL PERFORMANCE OF MULTI-LAYER SILICON MICROCHANNEL HEAT SINKS

The objective is to optimize the configuration sizes and thermal performance of a multi-layer silicon microchannel heat sink by the thermal resistance network model. The effect of structural parameter on the thermal resistance is analyzed by numercal simulation. Taking the thermal resistance as an objective function, a non-linear and multi-constrained optimization model are proposed for the silicon microchannel heat sink in electronic chips cooling. The sequential quadratic programming method is used to do the optimization design of the configuration sizes of the microchannel. For the heat sink with the size of 20 mm x 20 mm and the power of 400 W, the optimized microchannel number, layer, height, and width are 40, and 2, 2.2 mm, and 0.2 mm, respectively, and its corresponding total thermal resistance for whole microchannel heat sink is 0.0424 K/W.