DT2CAM: A Decision Tree to Content Addressable Memory Framework

Decision trees are powerful tools for data classification. Accelerating the decision tree search is crucial for on-theedge applications with limited power and latency budget. In this article, we propose a content-addressable memory compiler for decision tree inference acceleration. We propose a novel '' adaptiveprecision '' scheme that results in a compact implementation and enables an efficient bijective mapping to ternary content addressable memories while maintaining high inference accuracies. We also develop a resistive-based functional synthesizer to map the decision tree to resistive content addressable memory arrays and perform functional simulations for energy, latency, and accuracy evaluations. We study the decision tree accuracy under hardware non-idealities including device defects, manufacturing variability, and input encoding noise. We test our framework on various decision tree datasets including Give Me Some Credit, Titanic, and COVID-19. Our results reveal up to 42.4% energy savings and up to 17.8x better energy-delay-area product compared to the state-ofart hardware accelerators, and up to 333 million decisions per sec for the pipelined implementation.

Automated summary

This article proposes a content-addressable memory compiler for decision tree inference acceleration, and investigates the accuracy of decision tree under hardware non-idealities. Experimental results show significant improvements in energy consumption, latency, and accuracy with this framework.