Loss Analysis of a 24.4%-Efficient Front-Junction Silicon Heterojunction Solar Cell and Opportunity for Localized Contacts

Silicon heterojunction (SHJ) solar cells have recently reached power conversion efficiencies above 25% with various device architectures and with industrial size (>200 cm(2)) wafers. Yet, for an accurate assessment of the efficiency potential and further development of the technology, the identification of high-performing device configurations, and their detailed analysis is still vital. In this work, we first present an overview of our lab-scale (4 cm(2)) front-junction cells based on n-type wafers with a 24.44% certified efficiency. We report on the key improvements compared with our previously reported devices (i.e., thinner front-side silicon layers and low refractive index rear reflector). Then, we present a detailed power loss analysis, showing that parasitic absorption in the front layer-stack remains a major source of loss despite the recent improvements. Accordingly, we investigate next approaches to circumvent this loss, such as localization of the highly absorbing front layers and switching to a rear-junction architecture. Using numerical calculations, we show that the front-junction configuration can benefit from an efficiency gain of 0.3%(abs) with contact localization if considerably low contact resistivities (<20m Omega center dot cm(2)) are realized for the p-type contact. Even larger gain in efficiency can be achieved by simultaneously switching to a rear-junction architecture and localizing the n-type contact with contact resistivities that are relatively accessible with the current state of the art (up to 0.7%(abs) gain for <20 m Omega center dot cm(2)). Finally, we propose a simple fabrication method for contact localization using shadow masks during depositions of the front-side layers and demonstrate proof-of-concept cells with localized contacts.

Automated summary

Silicon heterojunction (SHJ) solar cells have achieved power conversion efficiencies above 25% with various device architectures and industrial size wafers. However, to accurately assess efficiency potential and further develop the technology, the identification and detailed analysis of high-performing device configurations are crucial. This study presents lab-scale front-junction cells with certified efficiency of 24.44% and improvements in front-side silicon layers and rear reflector. Power loss analysis reveals that parasitic absorption in the front layer-stack remains a major source of loss. Approaches like localization of highly absorbing front layers and switching to a rear-junction architecture are suggested to circumvent this loss.