Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts

Local geometric control of basic synthesis parameters, such as elemental composition, is important for bottom-up synthesis and top-down device definition on-chip but remains a significant challenge. Here, we propose to use lithographically defined metal stacks for regulating the surface concentrations of freely diffusing synthesis elements on compound semiconductors. This is demonstrated by geometric control of Indium droplet formation on Indium Arsenide surfaces, an important consequence of incongruent evaporation. Lithographic defined Aluminium/Palladium metal patterns induce well-defined droplet-free zones during annealing up to 600 & DEG;C, while the metal patterns retain their lateral geometry. Compositional and structural analysis is performed, as well as theoretical modelling. The Pd acts as a sink for free In atoms, lowering their surface concentration locally and inhibiting droplet formation. Al acts as a diffusion barrier altering Pd's efficiency. The behaviour depends only on a few basic assumptions and should be applicable to lithography-epitaxial manufacturing processes of compound semiconductors in general. Lithographic metal patterns are used to control the formation of large droplets that naturally occur during the heating of compound semiconductors. The general concept opens a new way to steer bottom-up synthesis across the surface of a chip.

Automated summary

This study proposes the use of lithographically defined metal stacks to regulate the surface concentrations of freely diffusing synthesis elements on compound semiconductors. The geometric control of Indium droplet formation on Indium Arsenide surfaces is achieved, and the behaviours of Aluminium and Palladium as flux control agents are investigated. The study demonstrates that lithographic metal patterns can be used to control the formation of large droplets during the heating of compound semiconductors, providing a new way to steer bottom-up synthesis on-chip.