4.7 Article

Ductile deformation and subsurface damage evolution mechanism of silicon wafer induced by ultra-precision grinding process

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TRIBOLOGY INTERNATIONAL
卷 189, 期 -, 页码 -

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ELSEVIER SCI LTD
DOI: 10.1016/j.triboint.2023.108879

关键词

Wafer self-rotation grinding; Silicon; Multiple nanoscratch; Subsurface defects; Damage evolution

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This work explores the mechanism of ductile deformation and subsurface damage evolution of silicon wafers during the ultra-precision grinding process. It provides insights into the phase transition properties and atomic-scale subsurface defects of ground silicon wafers. The influence of abrasive interactions on subsurface deformation is investigated using nanoscratch tests.
In the field of advanced packaging, large-size silicon wafers are usually thinned by ultra-precision grinding technology relying on the process of workpiece self-rotation. However, the damage caused by mechanical material removal deteriorates the wafer surface flatness and die strength, while its atomic-scale formation principle has yet to be revealed. This work explores the ductile deformation and subsurface damage evolution mechanism of silicon wafer during the ultra-precision grinding process. Some grinding tests are first conducted using different diamond wheels. The surface topography and energy dispersive spectroscopy (EDS) mapping of ground wafers are measured by scanning electron microscope (SEM). The phase transition properties of the ground silicon wafer are confirmed via Raman spectrum. Next, the specimen of groove cross-section is fabricated and its morphology is examined via transmission electron microscopy (TEM) to analyze the subsurface damage characteristics. The subsurface defects at the atomic scale, involving amorphous layer, dislocations, stacking faults and lattice distortions, are observed. Due to its controllable load and similarity of the cutting motion, nanoscratch is utilized for investigating the influence of abrasive interactions on subsurface deformation during the grinding process. Thus, a series of multiple nanoscratch tests are performed in both varied and constant force modes. The material removal behaviors under different scratching conditions are illustrated. This work provides a fundamental understanding of developing a high-efficiency and low-damage thinning method for 12-inch silicon wafers.

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