Sub-5 nm Gate-Length Monolayer Selenene Transistors

Two-dimensional (2D) semiconductors are being considered as alternative channel materials as silicon-based field-effect transistors (FETs) have reached their scaling limits. Recently, air-stable 2D selenium nanosheet FETs with a gate length of 5 & mu;m were experimentally produced. In this study, we used an ab initio quantum transport approach to simulate sub-5 nm gate-length double-gate monolayer (ML) selenene FETs. When considering negative-capacitance technology and underlap, we found that 3 nm gate-length p-type ML selenene FETs can meet the 2013 ITRS standards for high-performance applications along the armchair and zigzag directions in the 2028 horizon. Therefore, ML selenene has the potential to be a channel material that can scale Moore's law down to a gate length of 3 nm.

Automated summary

In this study, an ab initio quantum transport approach was used to simulate sub-5 nm gate-length double-gate monolayer selenene FETs. The research found that 3 nm gate-length p-type ML selenene FETs, when considering negative-capacitance technology and underlap, can meet the 2013 ITRS standards for high-performance applications. Therefore, selenene has the potential to scale Moore's law down to a gate length of 3 nm.