An approach for extracting the SiC/SiO2 SiC MOSFET interface trap distribution and study during short circuit

The high trap density at the SiC/SiO2 interface is still the major reliability issue of silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs). In this paper, we analyse the influence of the channel region and JFET region on the C-V curve from the band perspective. We proposed an approach to extract the oxide interface characteristics of a SiC MOSFET by fitting the measured C-V characteristic curve with the TCAD simulated curve. Then, the extracted SiC/SiO2 interface characteristics were verified by fitting the measured and simulated I-V curves and threshold voltages (VTH) at different lattice temperatures. Next, the extracted interface characteristics and the fixed interface charge were separately added to the TCAD model for comparison of the short-circuit simulations. It was found that the former model failed earlier than the latter and that the peak short-circuit current value was lower. The causes of these two phenomena are attributed to the different leakage degrees of the hole current in the Pbase region below the channel caused by interface traps and the difference in the channel mobility, respectively. Last, according to current shunt theory, P-type blocks were added below the JFET area to reduce the current during a short-circuit transient, thus improving the capacity to withstand a short circuit by approximately 22.4%.

Automated summary

This paper analyzes the influence of the channel region and JFET region on the C-V curve of SiC MOSFETs and proposes a method to extract the SiC/SiO2 interface characteristics by fitting the measured C-V curve with the TCAD simulated curve. The extracted interface characteristics are validated by comparing the measured and simulated I-V curves and threshold voltages (VTH) at different lattice temperatures. The extracted interface characteristics and fixed interface charge are then added to the TCAD model for short-circuit simulations, which show that the former fails earlier and has a lower peak short-circuit current due to the different leakage degrees of the hole current and the difference in channel mobility. Finally, P-type blocks are added below the JFET area to reduce the current during a short-circuit transient, improving the capacity to withstand a short circuit by approximately 22.4%.