期刊
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING
卷 162, 期 -, 页码 -出版社
ELSEVIER SCI LTD
DOI: 10.1016/j.mssp.2023.107488
关键词
Cobalt silicide; Surface preparation; Agglomeration; Nucleation
In microelectronics, the nucleation of cobalt silicide CoSi2 in small dimensions is difficult, but CoSi2 based contacts are still interesting for specific devices in 65 nm technology. The surface preparation of the Si substrate before Co deposition can influence the formation of cobalt silicide phases. Different surface preparations and Soft Sputter Etch processes have been applied on Si(100) wafers before the deposition of Co and TiN layers, resulting in different formation temperatures and crystalline orientations for the Co silicide phases. The results highlight the influence of surface preparation on the formation and agglomeration of Co silicides, and its importance for integrating CoSi2 films in a 65 nm CMOS technology.
In microelectronics, despite a difficult nucleation of cobalt silicide CoSi2 in small dimensions, the CoSi2 based contacts remain interesting for some specific devices designed in 65 nm technology. Therefore, to promote the formation of CoSi2 in 65 nm technologies, it is possible to interfere on the formation of CoSi, that occurs during RTA1. To this end, the surface preparation of the Si substrate, before the Co deposition, may have an influence on the cobalt silicide phases formation. In this work, different surface preparations (SiCoNi, HF followed by SC1 and HF only), as well as several Soft Sputter Etch, SSE, processes have been applied on Si(100) wafers before the deposition of Co and TiN layers. Depending on the surface preparation, the formation temperatures and/or crystalline orientations for the Co silicide phases, including CoSi2, are different, as observed by XRD and/or EBSD. Four-point probes measurements also show a strong dependency of the CoSi2 agglomeration to the surface preparation scheme. These results highlight the influence of surface preparation on the Co silicides formation and agglomeration and its importance for the integration of CoSi2 films in a 65 nm CMOS technology.
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