Spatial and Polarization Division Multiplexing Harnessing On-Chip Optical Beam Forming

On-chip spatial and polarization multiplexing has emerged as a powerful strategy to boost the data transmission capacity of integrated optical transceivers. State-of-the-art multiplexers require accurate control of the relative phase or the spatial distribution among different guided optical modes, seriously compromising the optical transmission bandwidth and performance of the devices. To overcome this limitation, a new approach based on the coupling between guided modes in integrated waveguides and optical beams free-propagating on the chip plane is proposed. The engineering of the evanescent coupling between the guided modes and free-propagating beams allows spatial and polarization multiplexing with state-of-the-art performance. A two-polarization multiplexed link and a three-mode multiplexed link using standard 220-nm-thick silicon-on-insulator technology have been developed. The two-polarization link shows a measured -35 dB crosstalk bandwidth of 180 nm, while the three-mode link exhibits a -20 dB crosstalk bandwidth of 195 nm. These links are used to demonstrate error-free operation (bit-error-rate <10(-9)) in multiplexing and demultiplexing of two and three non-return-to-zero signals at 40 Gbps each, with power penalties below 0.08 and 1.5 dB for the two-polarization and three-mode links, respectively. The approach demonstrated for two polarizations and three modes is transferable to future implementation of more complex multiplexing schemes.

Automated summary

On-chip spatial and polarization multiplexing is proposed as an effective strategy to enhance the data transmission capacity of integrated optical transceivers. By manipulating the coupling between guided modes and free-propagating beams, spatial and polarization multiplexing with state-of-the-art performance is achieved. Two-polarization and three-mode multiplexed links are developed using standard silicon-on-insulator technology, demonstrating error-free operation at 40 Gbps with low power penalties. This approach can be applied to future implementation of more complex multiplexing schemes.