A 3.83-5.55 GHz high frequency resolution DCO with optimized switched-capacitor ladder and low-coupled eight-shaped transformer

A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched-capacitor (SC) ladder and a low-coupled eight-shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on-chip transformer, thus reducing quantization noise and phase noise. An eight-shaped transformer designed using two coils cross-connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180-nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is -120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is -191 dBc/Hz. The chip size is 0.294 mm(2).

Automated summary

This paper proposes a high frequency resolution digitally controlled oscillator (DCO) for wireless transceivers, which utilizes an optimized cascaded differential switched-capacitor (SC) ladder and a low-coupled eight-shaped transformer. The frequency resolution is further enhanced by reducing the electromagnetic coupling effect between the primary and secondary coils of the on-chip transformer, thereby reducing quantization noise and phase noise. The DCO achieves a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz, and exhibits a phase noise of -120.29 dBc/Hz at 1 MHz offset from the carrier frequency of 3.83 GHz. The power consumption of the DCO is 9.26 mA from a 1.8 V supply, and the figure of merit with tuning range is -191 dBc/Hz. The chip size is 0.294 mm².