4.8 Article

A Family of Single-Stage ACDC Converters Integrated Interleaved PFC and Resonant DCDC Circuits

期刊

IEEE TRANSACTIONS ON POWER ELECTRONICS
卷 38, 期 8, 页码 10026-10039

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2023.3278450

关键词

Family topologies; interleaved power factor correction (PFC); reduced bus voltage; resonant dc/dc; single-stage ac/dc

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This article proposes a new type of single-stage ac/dc converter that integrates interleaved power factor correction (PFC) and resonant dc/dc circuits to address the high bus issue of conventional boost or buck-boost PFC integrated resonant single-stage converters under high-voltage input. The proposed three interleaved PFC structures divide the ac input voltage into two parts by two capacitors before the rectifier bridge, omitting the need for two high-frequency power diodes and one filter capacitor. The reduced bus voltage can be obtained with fewer devices, achieving better zero-crossing performance of input current, increased circuit efficiency, and at least a 2.3% improvement in efficiency under 220V nominal input and 100W load conditions, all while maintaining reduced bus voltage and similar power factor values.
To address the high bus issue of conventional boost or buck-boost power factor correction (PFC) integrated resonant dc/dc type single-stage converters under high-voltage input, a family of single-stage ac/dc converters integrated interleaved PFC and resonant dc/dc circuits is proposed in this article. Unlike traditional solutions, the ac input voltage of the proposed three interleaved PFC structures is divided into two parts by two capacitors before the rectifier bridge. Thus, two high-frequency power diodes and one filter capacitor are omitted. Furthermore, the reduced bus voltage can be simultaneously obtained with fewer devices. Correspondingly, a better zero-crossing performance of input current can be achieved theoretically. Most importantly, the circuit efficiency also can be increased. Using the common LLC circuit as dc/dc stages, simulations in PSIM are performed to verify the improved zero-crossing of input current. To introduce the proposed converters, the operation principles, design considerations, experimental results, and related comparisons for the proposed structure II with LLC cell are presented comprehensively, achieving at least a 2.3% improvement in efficiency under 220 V nominal input and 100 W load conditions, while maintaining reduced bus voltage and similar PF values. In addition, the experimental results of the topology I and III are also given to prove the validity of the proposed family converters.

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