期刊
IEEE TRANSACTIONS ON MAGNETICS
卷 59, 期 8, 页码 -出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMAG.2023.3288400
关键词
Bloch line (BL) device; micromagnetics simulation; racetrack memory (RTM); SPICE simulation
This work assesses the performance of Bloch line (BL) racetrack memory (RTM) through circuit-level simulations. A micromagnetics-SPICE hybrid simulation framework is proposed to guarantee both computational efficiency and micromagnetics-level accuracy. The feasibility of multibit BL memory operations is demonstrated, and some crucial considerations in designing and optimizing the BL memory are addressed.
The Bloch line (BL) racetrack memory (RTM) has recently been proposed as a novel device to overcome the problems of the conventional domain wall (DW) RTM such as stochastic shift and high shift threshold current due to process-induced roughness. In this work, we assess the performance of BL RTM memory cells by conducting circuit-level simulations. A micromagnetics-SPICE hybrid simulation framework is proposed and implemented as an optimal solution to guarantee both computational efficiency and micromagnetics-level accuracy. The feasibility of multibit BL memory operations is demonstrated as the stochastic Landau-Lifshitz-Gilbert (s-LLG) and Monte-Carlo (MC) simulations are carried out at room temperature to take into account the temperature effect and process-induced device mismatch. Furthermore, some crucial considerations in designing and optimizing the BL memory are addressed.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据