4.6 Article

High-Density 3-D NAND Cell Array Design With Hybrid Bonding

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IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2023.3311419

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cell array; cell array; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; flash memory; common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); common source line (CSL); wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; wafer stacking; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding; hybrid bonding

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This study proposes a novel cell array structure suitable for hybrid bonding technology in 3-D NAND architecture, allowing for the removal of dummy cell area and increase in bit density. The proposed method for programming this structure utilizes the asymmetric GIDL phenomenon for string selection and inhibition, potentially improving V-PASS disturbance.
In this study, we propose a novel cell array structure suitable for hybrid bonding technology, which is considered one of the promising future technologies in 3-D NAND architecture. By dividing the common source line (CSL) in the cell array into multiple source lines (SLs), this structure allows for the removal of the dummy cell area that hinders the increase in bit density in a conventional cell array. Through the removal of dummy cells, the bit densities in nine-and 24-cell structures can be increased by 8% and 15%, respectively. As the proposed structure is not compatible with the conventional method in the program operation, we also propose a new programming method suitable for this structure and verify it through technology computer-aided design (TCAD) simulations. The proposed method can achieve string selection and inhibition by utilizing the asymmetric gate-induced drain leakage (GIDL) phenomenon at both ends of the string and is expected to improve V-PASS disturbance.

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