Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline

Thin-film transistor (TFT)-type synaptic devices with poly-Si channels have the benefits of compatibility with the CMOS process, high reliability, and low power consumption. However, it is challenging to determine the optimal operating conditions of TFT arrays in hardware-based neural networks (HNNs) due to the limited device characteristics. In this work, we design hardware-based ternary neural networks (TNNs) using TFT-type synaptic devices. The electrical characteristics of the TFT array are investigated, and the effects of leakage currents are analyzed on the inference accuracy of TNNs. Based on the analysis, systematic optimization of the operating conditions is conducted to mitigate the impact of the device variation on the current sum and to maximize the accuracy. This result offers important guidelines for designing and optimizing hardware-based TNNs with not only TFT-type synaptic devices but also transistor-type synaptic devices.

Automated summary

This work designs hardware-based ternary neural networks (TNNs) using TFT-type synaptic devices and analyzes the impact of leakage currents on the inference accuracy of TNNs. Based on the analysis, systematic optimization of the operating conditions is conducted to improve accuracy.