Hardware/Software Co-Design of Cryptographic SoC Based on RISC-V Virtual Prototype

Embedded hardware accelerator with limited resources is increasingly employed in security areas. To accelerate system-on-chip (SoC) design, an efficient HW/SW co-design approach and validation platform become extremely important. The Electronic System Level Simulator (ESL) based on SystemC is the primary solution for fast hardware modeling and verification. However, most existing simulators cannot achieve a better trade-off between accuracy and performance, and none of the specific ESL simulators are proposed for cryptographic SoCs. To this end, this brief proposes a virtual prototype (VP) with integrated cryptographic accelerators for a cryptographic SoC based on RISC-V to accelerate the functional and performance simulation of the SoC. The VP is designed as an extensible and configurable platform dedicated to cryptographic SoC using an efficient HW/SW co-design approach. To accurately emulate real hardware, the flexible AHB-TLM interface and core timing model are presented. Compared to the RTL simulation, our custom VP performs about 10-450 times faster than the RTL simulation, and the simulation error is only about 4%. Our code is available at https://github.com/LX-IC/VP.

Automated summary

This paper proposes a virtual prototype with integrated cryptographic accelerators for a cryptographic SoC based on RISC-V, to accelerate the functional and performance simulation of the SoC. The virtual prototype is designed using an efficient HW/SW co-design approach and features flexible interface and core timing model, achieving simulation speeds much faster than RTL simulation.