Effects of grinding-induced surface topography on the material removal mechanism of silicon chemical mechanical polishing

Ultra-precision thinning technology using workpiece self-rotational grinding followed by chemical mechanical polishing (CMP) is extensively applied in the integrated circuit manufacturing process, which enables to obtain large size ultra-thin silicon wafers with high material removal rate and low damage layer thickness. However, an in-depth understanding of the influence caused by ground surface topography on material removal mechanism in silicon CMP process has not been revealed yet. This work systematically investigates the contact characteristics of the wafer-pad interface and corrosion behaviors of the ground silicon wafer immersed in polishing solution. Firstly, some silicon wafers are ground using different wheels and subsequently polished. The material removal depth during the whole CMP process is measured. Then, the intrinsic model of polishing pad is determined via mechanical property tests. A finite element method is adopted to evaluate the contact status, displacement distortion and stress distribution at the contact region between pad and ground wafer surface. Moreover, the chemical reaction mechanism between ground silicon wafer and polishing solution is revealed by utilizing X-ray photoelectron spectroscopy and electrochemical analysis. The influence of wafer surface topography on corrosion resistance in CMP process is illustrated. Finally, corresponding experimental results are explained from an atomic scale by a ReaxFF reactive molecular dynamics simulation model. This presented study demonstrates the corrosion promotion principle of ground silicon wafer in CMP process.

Automated summary

This study systematically investigates the influence of ground surface topography on the material removal mechanism in the chemical mechanical polishing (CMP) process of ultra-thin silicon wafers. Through experiments and simulations, the contact characteristics between the wafer and polishing solution, the corrosion behaviors of the ground silicon wafer, and the influence of wafer surface topography on corrosion resistance are revealed. The study demonstrates the corrosion promotion principle of ground silicon wafer in the CMP process.