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Article
Computer Science, Information Systems
Mohammad Hassan et al.
Summary: The paper proposes using approximate computing-based algorithms on FPGAs for processing neural signals acquired from MEAs. By utilizing approximate computing, the system can achieve better performance in terms of system area, power consumption, and real-time processing latency at the cost of reduced output accuracy within certain bounds. Results show a speed enhancement of up to 37.6% in some approximate systems without a loss in accuracy.
Article
Computer Science, Hardware & Architecture
Yavar Safaei Mehrabani et al.
Summary: This paper presents a novel and efficient inexact Full Adder cell utilizing carbon nanotube field-effect transistor (CNFET) technology and two logic styles - conventional CMOS (C-COMS) and pass transistor logic (PTL). Extensive simulations at transistor level and application level demonstrate higher performance in terms of power-delay-area product (PDAP compared to latest designs. Application level simulations using MATLAB show the quality of output images in terms of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM). The proposed circuit shows significant improvement in power-delay-area-PSNR product (PDAPP) and power-delay-area-SSIM product (PDASP) compared to its counterparts.
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS
(2022)
Article
Engineering, Electrical & Electronic
Seyed Hossein Shahrokhi et al.
Summary: A novel inexact Full Adder cell based on carbon nanotube field-effect transistor technology is proposed and investigated through simulations under different conditions, with application to an image blending system. The results demonstrate superior performance of the proposed cell in various metrics at both transistor and application levels.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2022)
Article
Engineering, Electrical & Electronic
Aishani Misra et al.
Summary: This article compares and evaluates different adders based on various criteria and performance indicators, identifying the adder with the best performance. According to the simulation results, the proposed adder has the minimum delay, minimum area, and lowest leakage power.
IETE JOURNAL OF RESEARCH
(2022)
Article
Computer Science, Information Systems
Amr Mohammaden et al.
Summary: This paper proposes a ternary MAC unit design using CNTFET, which offers higher information processing within the same number of digits compared to binary systems. The designed MAC unit has higher performance, lower power consumption, and operates at a frequency of up to 300 MHz.
Article
Computer Science, Information Systems
Khamalesh Kumar Padmanabhan et al.
Summary: Binary multipliers play a crucial role in computation systems used in Digital Signal Processing (DSP) and Fast Fourier transform (FFT) applications. A high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplier is proposed in this research study to reduce computation time. The GD multiplier achieves competency in processing algorithms by grouping partial products and decomposing them, with final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic results in a higher speed in multiplication.
Review
Chemistry, Analytical
Mohammadreza Kolahdouz et al.
Summary: This paper reviews the basics, advantages, drawbacks, recent progress and advances of carbon-related nanomaterials and nanostructures in micro and nanoelectronics, optoelectronics, and biotechnology.
Article
Computer Science, Information Systems
Marco Schaarschmidt et al.
Summary: Power consumption has become a crucial factor in embedded system design, and early detection is necessary to reduce development costs and address the complexity of hardware components. This article proposes an approach using model-driven development to estimate power consumption in software application models during early development stages. The approach includes the use of simulation data and a novel in-the-loop concept to determine the impact of software applications and detect power-related misbehavior.
Article
Computer Science, Information Systems
Padmanabhan Balasubramanian et al.
Summary: This paper analyzes the usefulness of inaccurate computing for digital image blending and demonstrates that inaccurate addition can produce similar quality of blended images compared to accurate addition. A specific inaccurate adder, M-HERLOA, is found to be preferable from the perspectives of image quality, error metrics, and design metrics. Experimental results show that M-HERLOA enables significant reduction in delay, area, and power consumption compared to accurate adders in both FPGA and ASIC design environments.
Article
Engineering, Electrical & Electronic
Padmanabhan Balasubramanian et al.
Summary: This paper presents a high-speed and energy-efficient architecture for the carry look-ahead adder (CLA). Experimental results show that the proposed CLA achieves significant reductions in critical path delay, power, and power-delay product (PDP) compared to the conventional CLA, the conditional sum adder (CSA), the carry-select adder (CSLA), and the Kogge-Stone adder (KSA).
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
(2022)
Article
Computer Science, Information Systems
Furqan Zahoor et al.
Summary: The latest multiple valued logic circuits have shown potential for higher storage density compared to binary circuits, attracting attention for digital system designs. Carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) are considered suitable options for MVL circuit designs, with proposed designs demonstrating advantages in terms of reduced transistor count, decreased cell area, and lower power consumption. Additionally, the participation of RRAM provides non-volatility advantages.
Article
Engineering, Electrical & Electronic
Zahra Zareei et al.
Summary: Two novel approximate Full Adder cells with capacitive threshold logic using carbon nanotube field-effect transistor technology are presented in this paper. Extensive simulations are carried out to investigate the efficiency of the proposed cells at both application and transistor levels. The results show the superiority of the proposed cells compared to others, considering a compromise between application and hardware-level metrics.
MICROELECTRONICS JOURNAL
(2021)
Article
Computer Science, Information Systems
Weiqiang Liu et al.
Summary: Approximate computing using majority logic is proposed to enhance performance and reduce power consumption. Designs of approximate adders and multipliers are presented, utilizing compressors and complement bits. An influence factor evaluation method and a scheme for selecting complement bits are introduced as well.
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
(2021)
Article
Computer Science, Hardware & Architecture
Mohammad Mirzaei et al.
COMPUTERS & ELECTRICAL ENGINEERING
(2020)
Article
Engineering, Electrical & Electronic
Roghayeh Ataie et al.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2019)
Article
Engineering, Electrical & Electronic
Candy Goyal et al.
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
(2019)
Article
Computer Science, Hardware & Architecture
Qiang Xu et al.
IEEE DESIGN & TEST
(2016)
Article
Computer Science, Hardware & Architecture
Jinghang Liang et al.
IEEE TRANSACTIONS ON COMPUTERS
(2013)
Article
Engineering, Electrical & Electronic
Jie Deng et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2007)
Article
Engineering, Electrical & Electronic
Jie Deng et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2007)
Article
Computer Science, Artificial Intelligence
Z Wang et al.
IEEE TRANSACTIONS ON IMAGE PROCESSING
(2004)