A Calibration-Free Digital-to-Time Converter for Phase Interpolation-Based Fractional-N PLLs

In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 mu m CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 mu m CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of -117dBc/Hz@1 MHz and -138dBc/Hz@10 MHz, and the RMS jitter of 0.860ps. The area of the proposed FDIV is 60x245 mu m(2), and the power consumption is 1.356mW. The phase noise of the proposed FNPLL in the fractional division mode is just 2dB higher than that in the integer division mode.

Automated summary

This paper proposes a fractional frequency division phase-locked loop based on phase interpolation and implements it using the TSMC 0.11μm CMOS process. A digital time converter (DTC) module is added to reduce the fractional spurious by phase interpolation. The DTC module is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. The proposed FNPLL achieves low power consumption, high accuracy, and low phase noise in both fractional and integer division modes.