Design and Implementation of CNFET SRAM Cells by Using Multi-Threshold Technique

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies.

Automated summary

This paper presents a design of CNFET-based MT-SRAM using the leakage reduction mechanism. The leakage current during read/write operations is reduced by employing multi-threshold logic. High threshold transistors are inserted in a serial manner to the low threshold circuit, where they contribute to low sub-threshold current. Meanwhile, low threshold transistors improve circuit performance. The implementation of multi-threshold-based SRAM cells using CNFET helps to avoid the short channel effect and mobility degradation in CMOS devices with channel length below 32nm. The paper clearly demonstrates the performance improvement of the proposed SRAM cells with the mentioned technologies.