Device Physics of Vertical Static Induction Transistors

Vertical static induction transistors (SITs), with vertically arranged source, porous gate, and drain elec-trodes, were proposed in 1950s and have recently gained new attention because of their suitability as flexible substrates and for hybrid integration with light-emitting diodes. However, the understanding of them is hindered by Schottky gate leakage and relies on case-by-case simulations. Here, we derive concise expressions for the channel potential and current-voltage characteristics for ideal SITs, including the sub-threshold swing, threshold voltage, and above-threshold region. The theory is verified by two-dimensional device simulation and agrees well with the reported experimental results. An ideal SIT can be approxi-mated as a partially gated transistor in parallel with a resistance and needs a sub-500-nm pore diameter to exhibit sharp switching in transfer scanning and good saturation in output scanning. The proposed theo-ries connect the device structure and electrical characteristics of SITs concisely, and conclusions are also applicable to permeable base transistors.

Automated summary

Vertical static induction transistors (SITs) have gained new attention due to their suitability for flexible substrates and hybrid integration with light-emitting diodes. However, understanding of them has been hindered by Schottky gate leakage. In this study, concise expressions for the channel potential and current-voltage characteristics of ideal SITs are derived, and the theory is verified through simulation and experimental results. The proposed theories connect the device structure and electrical characteristics of SITs concisely.