Fabrication of Ultrasmall Si Encapsulated in Silicon Dioxide and Silicon Nitride as Alternative to Impurity Doping

Further miniaturization of complementary metal oxide semiconductor devices based on impurity-doped semiconductors is limited due to statistical fluctuation of the impurity concentration in very small volumes and dopant deactivation, increasing the resistance and power consumption. Based on density functional theory calculations and backed by experimental data, the nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) has been described recently. It explains the structure shift of low-doped single-crystalline Si nanowells (Si-NWs) with thicknesses <= 3 nm embedded in SiO2 (Si3N4) toward n-type (p-type) behavior. The influence of the anions is on the scale of a few nanometers, allowing for very steep p-n junctions without the drawbacks of impurity doping. The process to fabricate crystalline silicon (c-Si) NWs embedded in SiO2 and Si3N4, starting with silicon on insulator (SOI) across 15 x 15 mm(2) samples, is described. Four possible methods to fabricate Si-NWs by thinning down single-crystalline top-Si of an SOI substrate are evaluated in terms of reproducibility and surface roughness.

Automated summary

Recently, the nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) has been described, based on density functional theory calculations and experimental data. This model explains the structure shift of low-doped single-crystalline Si nanowells (Si-NWs) with thicknesses <= 3 nm embedded in SiO2 (Si3N4) towards n-type (p-type) behavior. The influence of anions allows for very steep p-n junctions without the drawbacks of impurity doping. The process to fabricate crystalline silicon (c-Si) NWs embedded in SiO2 and Si3N4 is described and evaluated in terms of reproducibility and surface roughness.