The IRDS predicts that the scaling of silicon-based MOSFETs will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V. Two-dimensional indium selenide (InSe) has been explored as a potential channel material for further miniaturization of electronic devices, but no 2D semiconductor-based FETs have shown better performance than silicon FETs. In this study, a FET with 2D InSe as the channel material is reported, operating at 0.5 V with record high transconductance and surpassing the performance of silicon FETs. Yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Low subthreshold swing and drain-induced barrier lowering are achieved in the InSe FETs, as well as low contact resistance and smaller energy-delay product than predicted for silicon.
The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. (1)). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS mu m(-1) and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Omega mu m is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.
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