相关参考文献
注意：仅列出部分参考文献，下载原文获取全部文献信息。
Article
Engineering, Electrical & Electronic
BitSystolic: A 26.7 TOPS/W 2b∼8b NPU With Configurable Data Flows for Edge Devices
Qing Yang et al.
Summary: The article introduces a neural processing unit based on a systolic array structure called BitSystolic, which can support numerical precision configuration in the range of 2-8 bits, fulfilling different requirements across mixed-precision models and tasks. The unit can also flexibly support data flows in various types of neural layers and achieve adaptive optimization of data reuse by switching between different modes.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2021)
Article
Instruments & Instrumentation
FRIC - a 50 μm pixel-pitch single photon counting ASIC with Pattern Recognition algorithm in 40nm CMOS technology
P. Otfinowski et al.
JOURNAL OF INSTRUMENTATION (2020)
Article
Computer Science, Information Systems
An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA
Rihards Novickis et al.
ELECTRONICS (2020)
分享论文
