期刊
INTEGRATION-THE VLSI JOURNAL
卷 90, 期 -, 页码 22-26出版社
ELSEVIER
DOI: 10.1016/j.vlsi.2023.01.001
关键词
Pseudo random number generator; Chaotic map; FPGA
This paper introduces a pseudo random number generator (PRNG) built with a chaotic map without fixed points using fixed-point arithmetic. The randomness of the generated binary sequences is tested using TestU01 statistical tests. Three multimodal benchmark functions are optimized using the proposed PRNG and compared with the standard random function in C. The paper also presents a hardware design of the PRNG on an FPGA.
A pseudo random number generator (PRNG) is built with a chaotic map without fixed points implemented using fixed-point arithmetic. The generated binary sequences by the PRNG pass all the TestU01 statistical tests to prove the randomness of the generated binary sequences. Three multimodal benchmark functions are optimized with the heuristic Differential Evolution (DE) using the proposed PRNG, and these are compared with the DE using the standard random function available in the C programming language. If the shuffling technique is added to the generated chaotic random sequences, both approaches give the same statistically solutions. A hardware design in FPGA of the PRNG also is shown.
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