Probing Gate Dielectrics for Two-Dimensional Electronics at Atomistic Scale Using Transmission Electron Microscope

Layered materials with thermodynamical stability and scalable atomic thickness provide a potential solution for insulators in 2-D electronics. The formation of high-quality van der Waals interfaces provides potential solutions to overcome the present limit of gate control. To enhance the reliability and robustness of the 2-D device, the investigation of degradation kinetics and fundamental physics of breakdown events of layered dielectrics at an atomistic scale is important. However, the sub-nanometer thickness of layered gate stacks and complex interface states affected by atomic/electronic structures of local defects, which makes the breakdown mechanism research challenging. Advanced characterization technique with simultaneous analysis of elements, energy, and structure at an atomistic scale is crucial. Transmission electron microscope (TEM) is such a powerful tool to analyze the morphology, chemical composition, crystal structure, and electronic structure. In this review, the breakdown mechanism of layered insulators is summarized and discussed in depth at the atomistic scale. The challenges, which are important for the development of layered gate insulators, are also discussed.

Automated summary

Layered materials offer potential solutions for insulators in 2-D electronics, but their sub-nanometer thickness and complex interface states present challenges for their study. Transmission electron microscopy is a powerful tool for analyzing their morphology, chemical composition, crystal structure, and electronic structure.