4.5 Article

Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2022.3213617

关键词

Circuit faults; Integrated circuit modeling; Graphics processing units; Logic gates; Adaptation models; Load modeling; Instruction sets; Fault simulation; heterogeneous; multiple GPUs; very large-scale circuits

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This paper proposes an adaptive multidimensional parallel fault simulation framework based on the CPU-GPU heterogeneous system. It addresses the challenges of path divergence, unbalanced workload, and poor scalability, and further accelerates by introducing a 4-D parallel architecture on multiple GPUs. Experimental results show that compared to the commercial tool, the fault simulator based on 8 GPUs achieves an average speedup of 105.7 times, and for millions of gate-level circuits, the fault simulator based on one GPU achieves a speedup of up to 25.9 times compared to the CPU single-threaded simulator.
Fault simulation is a critical component of the automatic test pattern generation (ATPG) tool, which is widely used in chip development. The CPU-GPU heterogeneous system can accelerate fault simulation. However, existing work faces the following challenges: 1) Path Divergence: The simulation path of different faults is not uniform, which leads to low parallel efficiency of different GPU threads; 2) Unbalanced Workload: The load of different computing units is not balanced, leading to serious differences in the execution time of each part; and 3) Poor Scalability: When the circuit scale increases, the GPU memory is limited and the simulation has strong structural dependence, which makes the simulation difficult. In this work, we propose an adaptive multidimensional parallel fault simulation framework based on the CPU-GPU heterogeneous system. We adaptively select different simulation approaches according to different circuit scales. In detail, we use the fanout-free region (FFR) grouping method to solve the problem of path divergence. We also use a combination of static and dynamic load balancing to tradeoff data handling and the execution time of each computing unit. We limit the queue length used in the GPU to improve the scalability of the simulation. To further accelerate, we propose the 4-D parallel architecture on multiple GPUs. Extensive experimental results show that our fault simulator based on 8 GPU is $105.7\times $ faster than the commercial tool on average. For tens of millions of gate-level circuits, our fault simulator based on one GPU is up to $25.9\times $ faster than the CPU single-threaded simulator.

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