相关参考文献
注意：仅列出部分参考文献，下载原文获取全部文献信息。An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination
Gicheol Shin et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2021)
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
Yunpeng Cai et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS
Van Loi Le et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2018)
Near-Threshold Voltage (NTV) Computing
Vivek De et al.
IEEE DESIGN & TEST (2017)
Variations in Nanometer CMOS Flip-Flops: Part I-Impact of Process Variations on Timing
Massimo Alioto et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2015)
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
Natsumi Kawai et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2014)
COPING WITH PARAMETRIC VARIATION AT NEAR-THRESHOLD VOLTAGES
Ulya R. Karpuzcu et al.
IEEE MICRO (2013)
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
Massimo Alioto
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2012)
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
Ronald G. Dreslinski et al.
PROCEEDINGS OF THE IEEE (2010)
分享论文
