Recent Developments and Prospects of Fully Recessed MIS Gate Structures for GaN on Si Power Transistors

For high electron mobility transistors (HEMTs) power transistors based on AlGaN/GaN heterojunction, p-GaN gate has been the gate topology commonly used to deplete the two dimensional electron gas (2-DEG) and achieve a normally-OFF behavior. But fully recessed MIS gate GaN power transistors or MOSc-HEMTs have gained interest as normally-OFF HEMTs thanks to the wider voltage swing and reduced gate leakage current when compared to p-GaN gate HEMTs. However the mandatory AlGaN barrier etching to deplete the 2-DEG combined with the nature of the dielectric/GaN interface generates etching-related defects, traps, and roughness. As a consequence, the threshold voltage (V-TH) can be unstable, and the electron mobility is reduced, which presents a challenge for the integration of a fully recessed MIS gate. Recent developments have been studied to solve this challenge. In this paper, we discuss developments in gate recess with low impact etching and atomic layer etching (ALE) alongside surface treatments such as wet cleaning, thermal or plasma treatment, all in the scope of having a surface close to pristine. Finally, different interfacial layers, such as AlN, and alternative dielectrics investigated to optimize the dielectric/GaN interface are presented.

Automated summary

For high electron mobility transistors (HEMTs) based on AlGaN/GaN heterojunctions, the commonly used p-GaN gate topology is being replaced by fully recessed MIS gate GaN power transistors or MOSc-HEMTs due to their wider voltage swing and reduced gate leakage current. However, the etching process used to deplete the 2-DEG and achieve a normally-OFF behavior results in defects, traps, and roughness, affecting the stability of the threshold voltage and electron mobility. This paper discusses recent developments in gate recess techniques and surface treatments to optimize the dielectric/GaN interface.