Fully fixed-point integrated digital circuit design of discrete memristive systems

In this paper, the fully fixed-point digital integrated circuits of discrete memristive systems are designed with very low circuit area cost, where the two-stage pipeline and multi-cycle architecture is employed. Firstly, the mathematical models of the discrete memristor and a memristor chaotic map are presented and dynamics are analyzed. Secondly, data flow design is carried out and the feasibility of the fixed-point model is discussed, which provides a foundation for the further circuit design. Thirdly, different architectures are designed and we get the optimal results. As a result, gate area of the discrete memristor is 40288 mu m2 and the equivalent gate counts are 4588, while gate area of the discrete memristor map is 40424 mu m2 and the equivalent gate counts are 4604. Moreover, a chaotic pseudo random sequence generator is designed and the NIST test is passed. It provides the foundation for the further applications of the discrete memristor and discrete memristor chaotic systems.

Automated summary

In this paper, fully fixed-point digital integrated circuits for discrete memristive systems are designed to have very low circuit area cost, using a two-stage pipeline and multi-cycle architecture. Mathematical models for the discrete memristor and a memristor chaotic map are presented and their dynamics are analyzed. Data flow design is carried out and the feasibility of the fixed-point model is discussed, providing a foundation for further circuit design. Different architectures are designed to obtain optimal results. Gate area and gate counts are provided for the discrete memristor and the discrete memristor map. Additionally, a chaotic pseudo random sequence generator is designed and passes the NIST test, laying the foundation for further applications of the discrete memristor and discrete memristor chaotic systems.