4.7 Article

Hysteretic behavior of all CVD h-BN/graphene/h-BN heterostructure field-effect transistors by interfacial charge trap

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SURFACES AND INTERFACES
卷 36, 期 -, 页码 -

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ELSEVIER
DOI: 10.1016/j.surfin.2022.102615

关键词

h-BN; graphene; h-BN heterostructure; Field-effect transistor (FET); Hysteresis; Charge trapping

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The electrical transport properties of graphene field-effect transistors (FETs) can be greatly enhanced when graphene is supported by a high-quality hexagonal boron nitride (h-BN) layer. Chemical vapor deposition (CVD) grown h-BN can have surface defects and impurities, which result in different electrical transport properties compared to mechanically exfoliated h-BN layers. Surface defects and impurities on the supporting h-BN layer induce p-doping and hysteresis in h-BN/graphene/h-BN FETs, which can be controlled by modulating a back-gate voltage. The presence of these defects and impurities allows for dynamic modulation of electrical charge states, making them useful for memristive devices or sensors.
Superior electrical transport properties of graphene field-effect transistors (FETs) can be achieved when graphene is supported by a high-quality hexagonal boron nitride (h-BN) layer. The h-BN layer can serve as a highperformance insulator for a graphene channel to achieve high carrier mobility and to minimize doping effects on graphene by screening out the interaction with a gate oxide substrate. However, chemical vapor deposition (CVD) grown h-BN can have surface defects and impurities unlike mechanically exfoliated h-BN layers, which can result in completely different electrical transport properties of graphene FETs. In this study, we fabricated all CVD h-BN/graphene/h-BN FETs to explore how surface defects and impurities on the supporting h-BN layer can influence electrical transport properties of graphene. The presence of surface defects and impurities on the supporting h-BN layer, as revealed by Raman spectroscopy analysis, resulted in significant p-doping and hysteresis in the h-BN/graphene/h-BN FETs. Hysteresis in the FETs was induced by charge carrier trapping at the surface defects and impurities of the h-BN layer, which can be controlled by modulating a back-gate voltage. Based on the charge trapping mechanism on the surface of the h-BN, electrical charge states in all CVD h-BN/ graphene/h-BN can be modulated dynamically by realizing two different resistance states ('trap' vs. 'release' states), which can be utilized as memristive devices or sensors.

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