Benchmarking quantum error-correcting codes on quasi-linear and central-spin processors

We evaluate the performance of small error-correcting codes, which we tailor to hardware platforms of very different connectivity and coherence: on a superconducting processor based on transmon qubits and a spintronic quantum register consisting of a nitrogen-vacancy center in diamond. Taking the hardware-specific errors and connectivity into account, we investigate the dependence of the resulting logical error rate on the platform features such as the native gates, native connectivity, gate times, and coherence times. Using a standard error model parameterized for the given hardware, we simulate the performance and benchmark these predictions with experimental results when running the code on the superconducting quantum device. The results indicate that for small codes, the quasi-linear layout of the superconducting device is advantageous. Yet, for codes involving multi-qubit controlled operations, the central-spin connectivity of the color centers enables lower error rates.

Automated summary

We evaluate the performance of small error-correcting codes tailored to different hardware platforms, taking into account hardware-specific errors and connectivity. We investigate the dependence of logical error rate on platform features and benchmark our predictions with experimental results. The results show that the quasi-linear layout of superconducting devices is advantageous for small codes, while the central-spin connectivity of color centers enables lower error rates for codes involving multi-qubit controlled operations.