期刊
ELECTRONICS
卷 11, 期 23, 页码 -出版社
MDPI
DOI: 10.3390/electronics11233846
关键词
charge-domain filter; charge redistribution technique; CMOS integrated circuit; gain enhancement; low hardware complexity; read-out integrated circuit
This article presents a gain-enhanced, low hardware complexity charge-domain read-out integrated circuit, achieved through sampled charge redistribution technique, saving die area and providing gain enhancement. The charge-domain discrete-time filter with inherent reconfigurability works effectively as an anti-aliasing filter.
A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In particular, a charge-domain discrete-time filter with inherent reconfigurability is a key building block, which can also act as an anti-aliasing filter before the analog-to-digital converter. The measurement results show good agreement with the intended frequency response. The proposed filter is implemented using a 0.11 mu m CMOS process and occupies 0.15 mm(2).
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