4.7 Article

UV-Nanoimprint and Deep Reactive Ion Etching of High Efficiency Silicon Metalenses: High Throughput at Low Cost with Excellent Resolution and Repeatability

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NANOMATERIALS
卷 13, 期 3, 页码 -

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MDPI
DOI: 10.3390/nano13030436

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metasurfaces; photonic sensors; nanopatterning

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In order to use metasurfaces in industrial applications, scalable and cost-effective fabrication techniques are needed to produce large-area patterns with sub-100 nm resolution. We demonstrate the use of UV-Nanoimprint Lithography and Deep Reactive Ion Etching (Bosch and Cryogenic) for this purpose. We describe robust processes for fabricating silicon rectangular pillars with high pattern fidelity. Metasurface lenses are fabricated to demonstrate the quality of the structures, achieving diffraction limited focusing and high efficiency for specific wavelengths. We also develop a process to smooth the characteristic sidewall surface roughness and show that it does not adversely affect the optical performance of the metasurface lenses.
As metasurfaces begin to find industrial applications there is a need to develop scalable and cost-effective fabrication techniques which offer sub-100 nm resolution while providing high throughput and large area patterning. Here we demonstrate the use of UV-Nanoimprint Lithography and Deep Reactive Ion Etching (Bosch and Cryogenic) towards this goal. Robust processes are described for the fabrication of silicon rectangular pillars of high pattern fidelity. To demonstrate the quality of the structures, metasurface lenses, which demonstrate diffraction limited focusing and close to theoretical efficiency for NIR wavelengths lambda is an element of (1.3 mu m, 1.6 mu m), are fabricated. We demonstrate a process which removes the characteristic sidewall surface roughness of the Bosch process, allowing for smooth 90-degree vertical sidewalls. We also demonstrate that the optical performance of the metasurface lenses is not affected adversely in the case of Bosch sidewall surface roughness with 45 nm indentations (or scallops). Next steps of development are defined for achieving full wafer coverage.

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