Poole-Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor

This work reports, for the first time, the phenomenon of lateral Poole-Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current-voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole-Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole-Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires.

Automated summary

This work reports the phenomenon of lateral Poole-Frenkel current conduction along the dielectric/Si interface of a silicon nanowire MOS transistor for the first time. This discovery has significant impact on device characteristic modeling and reliability, and introduces a new type of electronic device - the Poole-Frenkel emission MOS transistor. The PF-MOS utilizes the high defect state Si/dielectric interface layer as the conduction channel and is expected to have unique features.